This invention relates to a vertical double-diffused metal oxide semiconductor field effect transistor for use in a power semiconductor device and, in particular, to a vertical double-diffused metal oxide semiconductor field effect transistor with a low breakdown voltage.
Metal oxide semiconductor field effect transistors (hereinafter referred to as "MOSFETs") are used as elements for use in a power semiconductor device in place of bipolar transistors because of superiority over switching speed or the like. Such MOSFETs are classified into double-diffused self-aligned MOSFETs (hereinafter referred to as "DSAMOSFETs") and vertical double-diffused MOSFETs (hereinafter referred to as "VDMOSFETs"). The VDMOSFETs are used in the power semiconductor device for ease of of workability and so on.
In general, a power semiconductor device comprises a plurality of VDMOSFETs which have the structure as follows. The semiconductor device comprises an N.sup.+ -type silicon substrate where "N.sup.+ " represents a high N-type impurity concentration. The N.sup.+ -type silicon substrate has a main or upper surface on which an N.sup.- -type epitaxial layer is formed where "N.sup.- " represents a low N-type impurity concentration. The N.sup.- -type epitaxial layer has a predetermined film thickness. The epitaxial layer has a surface on which a gate oxide layer and a gate electrode are formed in this order. The gate oxide layer has a predetermined thickness. The gate electrode consists of an N.sup.+ -type polysilicon having a predetermined thickness. The gate electrode (and the gate oxide layer) has a plurality of polygonal opening windows each of which has a desired form and which are regularly arranged to each other. The N.sup.+ -type epitaxial layer has therefore a plurality of partial surfaces which are exposed through the polygonal opening windows. In the partial surfaces of the N.sup.+ -type epitaxial layer are formed a plurality of P.sup.+ -type base regions with the base regions self-aligned to the polygonal opening windows or edge portions of the gate electrode, where "P.sup.+ " represents a high P-type impurity concentration. In the partial surfaces of the N.sup.+ -type epitaxial layer are formed a plurality of N.sup.+ -type source regions each of which is annular in shape. That is, each of the N.sup.+ -type source regions has one end which is self-aligned to the edge portions of the gate electrode. The semiconductor device comprises the VDMOSFETs which are formed in the polygonal opening windows. The VDMOSFETs comprise the P.sup.+ -type base regions and the N.sup.+ -type source regions, respectively, and comprise the gate electrode in common. The P.sup.+ -type base regions have a plurality of surfaces which are exposed near central portions of the polygonal opening windows. In other words, in the surfaces of the P.sup.+ -type base regions in the polygonal opening windows, the N.sup.+ -type source regions are not formed in entire surfaces of the polygonal opening windows but are formed in partial surfaces of the polygonal opening windows that have a predetermined width at the edge portions of the gate electrode.
On the gate electrode and the polygonal opening windows covers an interlayer insulating layer having a plurality of contact holes which reach the P.sup.+ -type base regions and the N.sup.+ -type source regions formed in the polygonal opening windows. On the interlayer insulating layer is formed a source electrode which electrically connects to all of the P.sup.+ -type base regions and the N.sup.+ -type source regions through the contact holes. An N-type drain region is formed in the VDMOSFETs in common and is composed of the N.sup.- -type epitaxial layer and the N.sup.+ -type silicon substrate. The N.sup.+ -type silicon substrate has a bottom or back surface which is opposite to the main surface thereof and on which a drain electrode is formed with the drain electrode electrically connected to the N.sup.+ -type silicon substrate. As described above, the power semiconductor device comprises the VDMOSFETs which are equal in number to the polygonal opening windows and which are electrically connected to each other in parallel.
Each of the P.sup.+ -type base regions has a base junction depth which is defined by a vertical base junction depth X.sub.jb in a vertical direction and a horizontal base junction depth X.sub.jb,1 in a horizontal direction beneath the gate electrode in the edge portions of the gate electrode. The horizontal base junction depth X.sub.jb,1 is about 0.8 times as large as the vertical base junction depth X.sub.jb (namely, X.sub.jb,1 .apprxeq.0.8X.sub.jb). On the other hand, each of the N.sup.+ -type source regions has a source junction depth which is defined by a vertical source junction depth X.sub.js in a vertical direction and a horizontal source junction depth X.sub.js,1 in a horizontal direction beneath the gate electrode in the edge portions of the gate electrode. The vertical source junction depth X.sub.js is shallower than the vertical base junction depth X.sub.jb (namely, X.sub.js &lt;X.sub.jb). The horizontal source junction depth X.sub.js,1 is about 0.8 times as large as the vertical source junction depth X.sub.js (namely, X.sub.js .apprxeq.0.8X.sub.js). Each VDMOSFET has a channel region which is a part of the P.sup.+ -type base region directly connected to the gate oxide layer beneath the gate electrode. The channel region has a channel length which is about equal to the horizontal base junction depth X.sub.jb,1 minus the horizontal source junction depth X.sub.js,1 (namely, X.sub.jb,1 -X,.sub.js,1). The gate electrode has a gate electrode length L.sub.G which is equal to the shortest distance between two opening windows adjacent to one another. If gate electrode length L.sub.G is longer than twice of the horizontal base junction depth X.sub.jb,1 (namely, L.sub.G &gt;2X.sub.jb,1), the VDMOSFETs are formed in the gate electrode.
Each of the opening windows in the gate electrode has the shape which is generally classified into a square and a regular hexagon. A gate electrode having square shaped opening windows have been disclosed in Japanese Unexamined Patent Prepublication No. 132684/77 issued on Nov. 7, 1977. The square shaped opening windows are arranged so that each of the square opening windows has a center which is positioned on each of lattice points in a two-dimensional square lattice having a desired lattice interval. Each of the square shaped opening windows has four sides which are parallel to the square lattice. In addition, the gate electrode having the square shaped opening windows may be modified into a gate electrode having octagonal shaped open windows. Such a gate electrode is disclosed in U.S. Pat. No. 5,016,066 which issued on May 14, 1991 to Mitsuasa Takahashi for assignment to the present assignee. A gate electrode having regular hexagonal shaped open windows is disclosed in U.S. Pat. No. 5,008,725 issued on Apr. 16, 1991. The regular hexagonal shaped open windows are arranged with close-packed. Both of U.S. Pat. No. 5,016,066 and U.S. Pat. No. 5,008,725 propose VDMOSFETs having a high breakdown voltage BV.sub.DSS where BV.sub.DSS represents a breakdown voltage between the drain regions and the source regions when the source and the gate electrodes are short-circuited. Accordingly, contrivance is made as regards a distribution of impurity concentration in the drain regions beneath the gate electrode and so on.
In the manner which will later be described, conventional VDMOSFETs are disadvantageous in that it is difficult to decrease on-resistance per unit area. As a result, it is difficult to improve switching speed and current density in the power semiconductor device which comprises the conventional VDMOSFETs each having a low breakdown voltage.